Transmitting circuit, semiconductor apparatus and semiconductor system configured to use the transmitting circuit

ABSTRACT

A transmitting circuit may include a clock generation circuit and a serializer. The clock generation circuit may generate a plurality of output clock signals by performing an emphasis operation for a plurality of clock signals based on a plurality of data. The serializer may output the plurality of data as output data in synchronization with the plurality of output clock signals.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean application number 10-2018-0044301, filed on Apr. 17, 2018, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety.

BACKGROUND 1. Technical Field

Various embodiments generally relate to an integrated circuit technologyand, more particularly, to a semiconductor apparatus and a semiconductorsystem.

2. Related Art

Electronic apparatuses may consist of a large number of electroniccomponents. Among the electronic apparatuses, a computer system mayconsist of many electronic components which are constructed bysemiconductors. Semiconductor apparatuses which construct a computersystem may transmit data in synchronization with a clock, and performserial communication. In order to quickly process a large amount of datain the semiconductor apparatuses, each of the semiconductor apparatusesreceives data inputted in series from another semiconductor apparatus,and converts the received data into a parallel type. Also, each of thesemiconductor apparatuses may convert internal data of a parallel typeinto a serial type, and output the converted data to anothersemiconductor apparatus. That is to say, each of the semiconductorapparatuses may include a serializer which converts data of a paralleltype into data of a serial type, to perform serial communication througha data bus.

It is the norm that the serializer has a configuration to sequentiallyoutput a plurality of data in synchronization with a clock. Currently,computer systems and semiconductor apparatuses tend to be developedtoward a high speed operation and low power consumption. As theoperating speed of a system is increased, the speed of a clock isgradually increased, and, as a system consumes low power, the amplitudesof the clock and data are decreased. Therefore, a serializer capable ofprecisely converting data in step with the recent technical trend isdemanded in the art.

SUMMARY

In an embodiment, a transmitting circuit includes a clock generationcircuit, and a serializer. The clock generation circuit may beconfigured to generate a plurality of output clock signals by performingan emphasis operation for at least one among a plurality of clocksignals based on at least one among a plurality of data. The serializermay be configured to output the plurality of data as output data insynchronization with the plurality of output clock signals.

In an embodiment, a transmitting circuit includes a serializer, and aclock generation circuit. The serializer may be configured to outputn{circumflex over ( )}th data in synchronization with a first outputclock signal, output (n+1){circumflex over ( )}th data insynchronization with a second output clock signal, output(n+2){circumflex over ( )}th data in synchronization with a third outputclock signal, and output (n+3){circumflex over ( )}th data insynchronization with a fourth output clock signal. The clock generationcircuit may be configured to generate the first output clock signal, thesecond output clock signal, the third output clock signal and the fourthoutput clock signal from a first clock signal, a second clock signal, athird clock signal and a fourth clock signal based on the n{circumflexover ( )}th data, the (n+1){circumflex over ( )}th data, the(n+2){circumflex over ( )}th data and the (n+3){circumflex over ( )}thdata.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a configuration of a semiconductorsystem in accordance with an embodiment.

FIG. 2 is a diagram illustrating a configuration of a transmittingcircuit in accordance with an embodiment.

FIG. 3 is a diagram illustrating a configuration of the clock emphasiscircuit shown in FIG. 2.

FIG. 4 is a timing diagram to assist in the explanation of the operationof the transmitting circuit in accordance with the embodiment.

FIG. 5 is a diagram illustrating output data outputted from atransmitting circuit in an ideal case, absent using a transmittingcircuit of the present disclosure, and using a transmitting circuit ofthe present disclosure.

DETAILED DESCRIPTION

Hereinafter, a transmitting circuit which may be for improving a dataeye, a semiconductor apparatus and a semiconductor system using thetransmitting circuit will be described below with reference to theaccompanying drawings through various examples of embodiments.

FIG. 1 is a diagram illustrating a representation of an example of theconfiguration of a semiconductor system 1 in accordance with anembodiment. In FIG. 1, the semiconductor system 1 may include a firstsemiconductor apparatus 110 and a second semiconductor apparatus 120.The first semiconductor apparatus 110 may provide various controlsignals which are necessary for the second semiconductor apparatus 120to operate. The first semiconductor apparatus 110 may include variouskinds of apparatuses. For example, the first semiconductor apparatus 110may be a host apparatus such as a central processing unit (CPU), agraphic processing unit (GPU), a multimedia processor (MMP), a digitalsignal processor, an application processor (AP) and a memory controller,etc. Also, the first semiconductor apparatus 110 may be a test apparatusor test equipment for testing the second semiconductor apparatus 120.

The second semiconductor apparatus 120 may be, for example, a memoryapparatus, and the memory apparatus may include a volatile memory or anonvolatile memory. The volatile memory may include an SRAM (staticRAM), a DRAM (dynamic RAM) or an SDRAM (synchronous DRAM), and thenonvolatile memory may include a ROM (read only memory), a PROM(programmable ROM), an EEPROM (electrically erasable and programmableROM), an EPROM (electrically programmable ROM), a flash memory, a PRAM(phase change RAM), an MRAM (magnetic RAM), an RRAM (resistive RAM) oran FRAM (ferroelectric RAM), etc.

The first and second semiconductor apparatuses 110 and 120 may becoupled with each other through a signal transmission line 130. Thefirst semiconductor apparatus 110 may include a pad 111, and the pad 111may be coupled with the signal transmission line 130. The secondsemiconductor apparatus 120 may include a pad 121, and the pad 121 maybe coupled with the signal transmission line 130. The signaltransmission line 130 may be a channel, a link or a bus. In anembodiment, the signal transmission line 130 may be a data transmissionline, and a signal to be transmitted through the signal transmissionline 130 may be data DQ.

The first semiconductor apparatus 110 may include a transmitting circuit(TX) 112 and a receiving circuit (RX) 113. The transmitting circuit 112may transmit data DQ to the second semiconductor apparatus 120 throughthe signal transmission line 130, based on internal data DI1 of thefirst semiconductor apparatus 110. The receiving circuit 113 may receivedata DQ transmitted from the second semiconductor apparatus 120, throughthe signal transmission line 130, and generate internal data DI1.Similarly, the second semiconductor apparatus 120 may include atransmitting circuit (TX) 122 and a receiving circuit (RX) 123. Thetransmitting circuit 122 may transmit data DQ to the first semiconductorapparatus 110 through the signal transmission line 130, based oninternal data DI2 of the second semiconductor apparatus 120. Thereceiving circuit 123 may receive data DQ transmitted from the firstsemiconductor apparatus 110, through the signal transmission line 130,and generate internal data DI2.

The transmitting circuits 112 and 122 may transmit data DQ to the signaltransmission line 130 in synchronization with clock signals, and thereceiving circuits 113 and 123 may receive data DQ transmitted throughthe signal transmission line 130, in synchronization with clock signals.The transmitting circuits 112 and 122 may be a transmission clock signalTCK. The transmitting circuit 112 may output internal data DI1 as dataDQ in synchronization with the transmission clock signal TCK. Thetransmitting circuit 122 may output internal data DI2 as data DQ insynchronization with the transmission clock signal TCK. The receivingcircuits 113 and 123 may receive a reception clock signal RCK. Thereceiving circuit 113 may receive and/or sample data DQ transmittedthrough the signal transmission line 130, in synchronization with thereception clock signal RCK, and generate internal data DI1. Thereceiving circuit 123 may receive and/or sample data DQ transmittedthrough the signal transmission line 130, in synchronization with thereception clock signal RCK, and generate internal data DI2.

Data DQ to be transmitted through the signal transmission line 130, asserial type data, may be a data stream in which a plurality of data aresuccessively transmitted. The internal data DI1 and DI2 of the first andsecond semiconductor apparatuses 110 and 120 may be parallel type data.Each of the transmitting circuits 112 and 122 may include a serializerto convert the parallel type internal data DI1 and DI2 into serial typedata. Each of the receiving circuits 113 and 123 may include adeserializer to convert serial type data into the parallel type internaldata DI1 and DI2. The transmission clock signal TCK and the receptionclock signal RCK may include a plurality of clock signals which havedifferent phases. The transmitting circuits 112 and 122 may convert theparallel type internal data DI1 and DI2 into data DQ in synchronizationwith a plurality of clock signals which have different phases. Thereceiving circuits 113 and 123 may convert data DQ into the paralleltype internal data DI1 and DI2 in synchronization with a plurality ofclock signals which have different phases. While not shown, each of thefirst and second semiconductor apparatuses 110 and 120 may include aclock generation circuit for generating the transmission clock signalTCK and the reception clock signal RCK.

FIG. 2 is a diagram illustrating a representation of an example of theconfiguration of a transmitting circuit 200 in accordance with anembodiment. The transmitting circuit 200 may be applied as each of thetransmitting circuits 112 and 122 shown in FIG. 1. In FIG. 2, thetransmitting circuit 200 may receive a plurality of data and a pluralityof clock signals and generate output data DOUT. The plurality of data(i.e., Dn to Dn+3) may correspond to the internal data DI1 and DI2 shownin FIG. 1, the plurality of clock signals (i.e., ICK, QCK, ICKB, andQCKB) may correspond to the transmission clock signal TCK shown in FIG.1, and the output data DOUT may correspond to the data DQ transmittedthrough the signal transmission line 130 shown in FIG. 1. Thetransmitting circuit 200 may generate a plurality of output clocksignals by performing an emphasis operation for at least one among theplurality of clock signals based on at least one among the plurality ofdata. The transmitting circuit 200 may output the plurality of data asthe output data DOUT, respectively, in synchronization with theplurality of output clock signals. The transmitting circuit 200 mayperform the emphasis operation to improve and/or extend the eye and/orvalid window of the output data DOUT. The emphasis operation may be toextend the pulse widths of the plurality of clock signals and therebygenerate the plurality of output clock signals. The emphasis operationmay be to advance the phases of the rising edges of the plurality ofclock signals and thereby generate the plurality of output clocksignals. The transmitting circuit 200 may selectively perform theemphasis operation by monitoring and/or sensing the level of previousdata already outputted and the level of current data to be outputted.The emphasis operation may be performed for at least one clock signalamong the plurality of clock signals.

In FIG. 2, the transmitting circuit 200 may include a clock generationcircuit 210 and a serializer 220. The clock generation circuit 210 mayreceive a plurality of data and a plurality of clock signals andgenerate a plurality of output clock signals. The plurality of data mayinclude n{circumflex over ( )}th data Dn, (n+1){circumflex over ( )}thdata Dn+1, (n+2){circumflex over ( )}th data Dn+2 and (n+3){circumflexover ( )}th data Dn+3. ‘n’ may be an integer of 1 or more. The pluralityof clock signals may include a first clock signal ICK, a second clocksignal QCK, a third clock signal ICKB and a fourth clock signal QCKB.The plurality of output clock signals may include a first output clocksignal ICKO, a second output clock signal QCKO, a third output clocksignal ICKOB and a fourth output clock signal QCKOB. In FIG. 2, it isillustrated as an example that the serializer 220 is a 4:1 serializerand therefore each of the numbers of data and clock signals received bythe transmitting circuit 200 is 4. However, it is to be noted that theembodiments are not limited thereto and each of the numbers of data andclock signals may be changed variously depending on the configuration ofthe serializer 220. The first to fourth clock signals ICK, QCK, ICKB andQCKB may be clock signals which sequentially have a predetermined phasedifference. For example, the predetermined phase difference may be 90degrees. The first clock signal ICK may have a phase 90 degrees earlierthan the second clock signal QCK, and the second clock signal QCK mayhave a phase 90 degrees earlier than the third clock signal ICKB. Thethird clock signal ICKB may have a phase 90 degrees earlier than thefourth clock signal QCKB. The fourth clock signal QCKB may have a phase90 degrees earlier than the first clock signal ICK.

The word “predetermined” as used herein with respect to a parameter,such as a predetermined phase difference, means that a value for theparameter is determined prior to the parameter being used in a processor algorithm. For some embodiments, the value for the parameter isdetermined before the process or algorithm begins. In other embodiments,the value for the parameter is determined during the process oralgorithm but before the parameter is used in the process or algorithm.

The clock generation circuit 210 may generate the first to fourth outputclock signals ICKO, QCKO, ICKOB and QCKOB by performing an emphasisoperation for at least one among the first to fourth clock signals ICK,QCK, ICKB and QCKB based on at least one among the n{circumflex over( )}th to (n+3){circumflex over ( )}th data Dn, Dn+1, Dn+2 and Dn+3. Theserializer 220 may receive the n{circumflex over ( )}th to(n+3){circumflex over ( )}th data Dn, Dn+1, Dn+2 and Dn+3, and the firstto fourth output clock signals ICKO, QCKO, ICKOB and QCKOB generatedfrom the clock generation circuit 210. The serializer 220 may output then{circumflex over ( )}th data Dn as the output data DOUT insynchronization with the first output clock signal ICKO. The serializer220 may output the (n+1){circumflex over ( )}th data Dn+1 as the outputdata DOUT in synchronization with the second output clock signal QCKO.The serializer 220 may output the (n+2){circumflex over ( )}th data Dn+2as the output data DOUT in synchronization with the third output clocksignal ICKOB. The serializer 220 may output the (n+3){circumflex over( )}th data Dn+3 as the output data DOUT in synchronization with thefourth output clock signal QCKOB. For example, in the case where theoutput data DOUT includes a total of eight data, the serializer 220 mayoutput first and fifth data in synchronization with the first outputclock signal ICKO, output second and sixth data in synchronization withthe second output clock signal QCKO, output third and seventh data insynchronization with the third output clock signal ICKOB, and outputfourth and eighth data in synchronization with the fourth output clocksignal QCKOB.

The clock generation circuit 210 may include a data detecting circuit211 and a clock emphasis circuit 212. The data detecting circuit 211 mayreceive the n{circumflex over ( )}th to (n+3){circumflex over ( )}thdata Dn, Dn+1, Dn+2 and Dn+3 and generate emphasis control signalsEMP<1:4>. The data detecting circuit 211 may generate the emphasiscontrol signals EMP<1:4> by sensing the level of previously outputteddata and the level of data to be currently outputted. The emphasiscontrol signals EMP<1:4> may include a plurality of bits. Each of theemphasis control signals EMP<1:4> may determine whether to perform anemphasis operation for a clock signal allocated thereto. For example,the emphasis control signal EMP<1> may determine whether to perform anemphasis operation for the first clock signal ICK associated with then{circumflex over ( )}th data Dn, and the emphasis control signal EMP<2>may determine whether to perform an emphasis operation for the secondclock signal QCK associated with the (n+1){circumflex over ( )}th dataDn+1. The emphasis control signal EMP<3> may determine whether toperform an emphasis operation for the third clock signal ICKB associatedwith the (n+2){circumflex over ( )}th data Dn+2, and the emphasiscontrol signal EMP<4> may determine whether to perform an emphasisoperation for the fourth clock signal QCKB associated with the(n+3){circumflex over ( )}th data Dn+3. In an embodiment, the datadetecting circuit 211 may be implemented with software, hardware, or anycombination thereof.

The data detecting circuit 211 may determine a situation whereinter-symbol interference (ISI) severely occurs, based on then{circumflex over ( )}th to (n+3){circumflex over ( )}th data Dn, Dn+1,Dn+2 and Dn+3. The situation where inter-symbol interference severelyoccurs may result when a signal abruptly transitions to a high levelwhile being held at a low level and/or a high resistance state. Also,inter-symbol interference may severely occur when a signal transitionsto the other level while being held at one level of high and low levelsfor a predetermined time. The inter-symbol interference may retard thetransition time of data and thereby decrease the eye and/or valid windowof the data. In order to prevent the eye of data from being decreased bythe inter-symbol interference, the data detecting circuit 211 maygenerate the emphasis control signals EMP<1:4> when the transmittingcircuit 200 outputs first data having a high level as the output dataDOUT, such that an emphasis operation may be performed for a clocksignal with which the first data is synchronized. For example, whenfirst data (that is, the n{circumflex over ( )}th data Dn) has a highlevel and the output data DOUT is generated from the first data, thedata detecting circuit 211 may enable the emphasis control signal EMP<1>such that an emphasis operation for the first clock signal ICK may beperformed and thereby the first output clock signal ICKO may begenerated.

The data detecting circuit 211 may enable the emphasis control signalsEMP<1:4> when the transmitting circuit 200 outputs data of the otherlevel while successively outputting data having one level of high andlow levels by a threshold number of times, such that an emphasisoperation may be performed for a clock signal with which the data of theother level is synchronized. The threshold number of times may be, forexample, 3. For example, when the transmitting circuit 200 successivelyoutputs the (n+2){circumflex over ( )}th data Dn+2, the (n+3){circumflexover ( )}th data Dn+3 and the n{circumflex over ( )}th data Dn each ofwhich has a low level, as the output data DOUT, and the (n+1){circumflexover ( )}th data Dn+1 to be outputted next has a high level, the datadetecting circuit 211 may enable the emphasis control signal EMP<2> suchthat an emphasis operation for the second clock signal QCK may beperformed.

The clock emphasis circuit 212 may receive the first to fourth clocksignals ICK, QCK, ICKB and QCKB and the emphasis control signalsEMP<1:4> and generate the first to fourth output clock signals ICKO,QCKO, ICKOB and QCKOB. The clock emphasis circuit 212 may generate thefirst to fourth output clock signals ICKO, QCKO, ICKOB and QCKOB byperforming an emphasis operation for the first to fourth clock signalsICK, QCK, ICKB and QCKB based on the emphasis control signals EMP<1:4>.The emphasis operation may be an operation of extending the pulse widthsof the first to fourth output clock signals ICKO, QCKO, ICKOB and QCKOBin comparison with the first to fourth clock signals ICK, QCK, ICKB andQCKB or advancing the phases of the rising edges of the first to fourthoutput clock signals ICKO, QCKO, ICKOB and QCKOB in comparison with therising edges of the first to fourth clock signals ICK, QCK, ICKB andQCKB. The clock emphasis circuit 212 may use a clock signal which has aphase earlier than a clock signal being a target of an emphasisoperation, to perform the emphasis operation. For example, an emphasisoperation for the first clock signal ICK may be performed by using thefourth clock signal QCKB, and an emphasis operation for the second clocksignal QCK may be performed by using the first clock signal ICK. Anemphasis operation for the third clock signal ICKB may be performed byusing the second clock signal QCK, and an emphasis operation for thefourth clock signal QCKB may be performed by using the third clocksignal ICKB. The clock emphasis circuit 212 may selectively perform anemphasis operation for a clock signal requiring an emphasis operationamong the first to fourth clock signals ICK, QCK, ICKB and QCKB, basedon the emphasis control signals EMP<1:4>. A clock signal for which anemphasis operation is performed may be outputted as an output clocksignal by being increased in its pulse width or being advanced in itsphase, and a clock signal for which an emphasis operation is notperformed may be outputted as an output clock signal as it is.

FIG. 3 is a diagram illustrating a representation of an example of theconfiguration of the clock emphasis circuit 212 shown in FIG. 2. In FIG.3, the clock emphasis circuit 212 may include a gating signal generator310 and a clock driver 320. The gating signal generator 310 may receivethe emphasis control signals EMP<1:4> and the first to fourth clocksignals ICK, QCK, ICKB and QCKB. The gating signal generator 310 maygenerate first to fourth gating clock signals PICK, PQCK, PICKB andPQCKB based on the emphasis control signals EMP<1:4> and the first tofourth clock signals ICK, QCK, ICKB and QCKB. When the emphasis controlsignal EMP<1> is enabled, the gating signal generator 310 may output thefourth clock signal QCKB which has a phase earlier than the first clocksignal ICK, as the first gating clock signal PICK. When the emphasiscontrol signal EMP<2> is enabled, the gating signal generator 310 mayoutput the first clock signal ICK which has a phase earlier than thesecond clock signal QCK, as the second gating clock signal PQCK. Whenthe emphasis control signal EMP<3> is enabled, the gating signalgenerator 310 may output the second clock signal QCK which has a phaseearlier than the third clock signal ICKB, as the third gating clocksignal PICKB. When the emphasis control signal EMP<4> is enabled, thegating signal generator 310 may output the third clock signal ICKB whichhas a phase earlier than the fourth clock signal QCKB, as the fourthgating clock signal PQCKB. In an embodiment, the gating signal generator310 may be implemented with software, hardware, or any combinationthereof.

The clock driver 320 may receive the first to fourth clock signals ICK,QCK, ICKB and QCKB and the first to fourth gating clock signals PICK,PQCK, PICKB and PQCKB and generate the first to fourth output clocksignals ICKO, QCKO, ICKOB and QCKOB. The clock driver 320 may include afirst driver 321, a second driver 322, a third driver 323 and a fourthdriver 324. The first driver 321 may receive the first clock signal ICKand the first gating clock signal PICK, and generate the first outputclock signal ICKO by performing an emphasis operation for the firstclock signal ICK based on the first gating clock signal PICK. The seconddriver 322 may receive the second clock signal QCK and the second gatingclock signal PQCK, and generate the second output clock signal QCKO byperforming an emphasis operation for the second clock signal QCK basedon the second gating clock signal PQCK. The third driver 323 may receivethe third clock signal ICKB and the third gating clock signal PICKB, andgenerate the third output clock signal ICKOB by performing an emphasisoperation for the third clock signal ICKB based on the third gatingclock signal PICKB. The fourth driver 324 may receive the fourth clocksignal QCKB and the fourth gating clock signal PQCKB, and generate thefourth output clock signal QCKOB by performing an emphasis operation forthe fourth clock signal QCKB based on the fourth gating clock signalPQCKB.

In FIG. 3, the first driver 321 may include a first buffer circuit 331and a first emphasis circuit 341. The first buffer circuit 331 maybuffer the first clock signal ICK and output the first output clocksignal ICKO. The first buffer circuit 331 may be configured by an evennumber of inverters which are coupled in series. In FIG. 3, the firstbuffer circuit 331 may include first and second inverters IV1 and IV2.The first emphasis circuit 341 may receive the first gating clock signalPICK, and feed back the first output clock signal ICKO to the firstclock signal ICK based on the first gating clock signal PICK. The firstemphasis circuit 341 may invert the first output clock signal ICKO andfeed back the inverted signal to the first clock signal ICK, such thatan emphasis operation for the first clock signal ICK may be performed.The first emphasis circuit 341 may include a first control inverter CIV1which is turned on based on the first gating clock signal PICK. When thefirst gating clock signal PICK is enabled, the first control inverterCIV1 may invert the first output clock signal ICKO and couple theinverted signal with the first clock signal ICK.

The second driver 322 may include a second buffer circuit 332 and asecond emphasis circuit 342. The second buffer circuit 332 may bufferthe second clock signal QCK and output the second output clock signalQCKO. The second buffer circuit 332 may include third and fourthinverters IV3 and IV4. The second emphasis circuit 342 may receive thesecond gating clock signal PQCK, and feed back the second output clocksignal QCKO to the second clock signal QCK based on the second gatingclock signal PQCK. The second emphasis circuit 342 may invert the secondoutput clock signal QCKO and feed back the inverted signal to the secondclock signal QCK, such that an emphasis operation for the second clocksignal QCK may be performed. The second emphasis circuit 342 may includea second control inverter CIV2 which is turned on based on the secondgating clock signal PQCK. When the second gating clock signal PQCK isenabled, the second control inverter CIV2 may invert the second outputclock signal QCKO and couple the inverted signal with the second clocksignal QCK.

The third driver 323 may include a third buffer circuit 333 and a thirdemphasis circuit 343. The third buffer circuit 333 may buffer the thirdclock signal ICKB and output the third output clock signal ICKOB. Thethird buffer circuit 333 may include fifth and sixth inverters IV5 andIV6. The third emphasis circuit 343 may receive the third gating clocksignal PICKB, and feed back the third output clock signal ICKOB to thethird clock signal ICKB based on the third gating clock signal PICKB.The third emphasis circuit 343 may invert the third output clock signalICKOB and feed back the inverted signal to the third clock signal ICKB,such that an emphasis operation for the third clock signal ICKB may beperformed. The third emphasis circuit 343 may include a third controlinverter CIV3 which is turned on based on the third gating clock signalPICKB. When the third gating clock signal PICKB is enabled, the thirdcontrol inverter CIV3 may invert the third output clock signal ICKOB andcouple the inverted signal with the third clock signal ICKB.

The fourth driver 324 may include a fourth buffer circuit 334 and afourth emphasis circuit 344. The fourth buffer circuit 334 may bufferthe fourth clock signal QCKB and output the fourth output clock signalQCKOB. The fourth buffer circuit 334 may include seventh and eighthinverters IV7 and IV8. The fourth emphasis circuit 344 may receive thefourth gating clock signal PQCKB, and feed back the fourth output clocksignal QCKOB to the fourth clock signal QCKB based on the fourth gatingclock signal PQCKB. The fourth emphasis circuit 344 may invert thefourth output clock signal QCKOB and feed back the inverted signal tothe fourth clock signal QCKB, such that an emphasis operation for thefourth clock signal QCKB may be performed. The fourth emphasis circuit344 may include a fourth control inverter CIV4 which is turned on basedon the fourth gating clock signal PQCKB. When the fourth gating clocksignal PQCKB is enabled, the fourth control inverter CIV4 may invert thefourth output clock signal QCKOB and couple the inverted signal with thefourth clock signal QCKB.

FIG. 4 is a representation of an example of a diagram to assist in theexplanation of the operation of the transmitting circuit 200 inaccordance with an embodiment. The operations of the transmittingcircuit 200 and the semiconductor system 1 in accordance with theembodiments will be described below with reference to FIGS. 1 to 4. Itwill be exemplified that the first semiconductor apparatus 110 transmitseight data to the second semiconductor apparatus 120. In FIG. 4, BL1 maybe first data, BL2 may be second data, BL3 may be third data, BL4 may befourth data, BL5 may be fifth data, BL6 may be sixth data, BL7 may beseventh data, and BL8 may be eighth data. BL1 and BL5 may be then{circumflex over ( )}th data Dn, BL2 and BL6 may be the(n+1){circumflex over ( )}th data Dn+1, BL3 and BL7 may be the(n+2){circumflex over ( )}th data Dn+2, and BL4 and BL8 may be the(n+3){circumflex over ( )}th data Dn+3. BL1 is the first data, and mayhave a high level (“H”). For example, the rising edges of the firstclock signal ICK may be center-aligned with BL1 and BL5, the risingedges of the second clock signal QCK may be center-aligned with BL2 andBL6, the rising edges of the third clock signal ICKB may becenter-aligned with BL3 and BL7, and the rising edges of the fourthclock signal QCKB may be center-aligned with BL4 and BL8.

Since no data is outputted before BL1 is outputted and BL1 has the highlevel, the data detecting circuit 211 may enable the emphasis controlsignal EMP<1>. The gating signal generator 310 may generate the firstgating clock signal PICK from the fourth clock signal QCKB based on theemphasis control signal EMP<1>. The first emphasis circuit 341 of thefirst driver 321 may invert the first output clock signal ICKO based onthe first gating clock signal PICK, and couple the inverted signal withthe first clock signal ICK. Since the first output clock signal ICKO isa low level when the first gating clock signal PICK is enabled, a signalof a high level may be provided to the first clock signal ICK and thusan emphasis operation for the first clock signal ICK may be performed.Accordingly, the rising edge of the first output clock signal ICKO maybe generated earlier than the rising edge of the first clock signal ICK,and the first output clock signal ICKO may have a pulse width wider thanthe first clock signal ICK. In FIG. 4, the first output clock signalICKO may be enabled at a point of time earlier than the point of timeindicated by the dotted line. The serializer 220 may output BL1 as theoutput data DOUT in synchronization with the first output clock signalICKO of which phase is advanced in comparison with the first clocksignal ICK. Therefore, the eye and/or valid window of first output dataDQ1 may be increased by a period by which the phase of the first outputclock signal ICKO is advanced, and the first output data DQ1 having ahigh level may be precisely outputted. If BL1 is a low level and BL2 isa high level, since high level data to be outputted first is BL2, thedata detecting circuit 211 may enable the emphasis control signalEMP<2>, an emphasis operation for the second clock signal QCK may beperformed, and the eye and/or valid window of second output data DQ2 maybe increased.

However, since BL1 is a high level (“H”) and the next successivelyoutputted data BL2 is a low level (“L”) the data detecting circuit 211may sense that data of a low level is outputted after data of a highlevel is outputted less than a threshold number of times, and thus mightnot enable the emphasis control signal EMP<2> associated with BL2.Additionally, since all of BL2, BL3, BL4 and BL5 have low levels (“L”),the data detecting circuit 211 might not enable the emphasis controlsignals EMP<1:4>, and an emphasis operation for the first to fourthclock signals ICK, QCK, ICKB and QCKB might not be performed. Therefore,BL2 may be outputted as second output data DQ2 in synchronization withthe second output clock signal QCKO which has the same phase as thesecond clock signal QCK, and BL3 may be outputted as third output dataDQ3 in synchronization with the third output clock signal ICKOB whichhas the same phase as the third clock signal ICKB. BL4 may be outputtedas fourth output data DQ4 in synchronization with the fourth outputclock signal QCKOB which has the same phase as the fourth clock signalQCKB, and BL5 may be outputted as fifth output data DQ5 insynchronization with the first output clock signal ICKO which has thesame phase as the first clock signal ICK.

BL6 may have a high level “H,” and the data detecting circuit 211 maysense that data having low levels have been successively outputtedbefore BL6 is outputted. Since BL2 to BL5 are the low levels (“L”) andBL6 is the high level (“H”), the data detecting circuit 211 may sensethat data of a high level is outputted after data of a low level isoutputted at least a threshold number of times, and may enable theemphasis control signal EMP<2> associated with BL6. The gating signalgenerator 310 may generate the second gating clock signal PQCK from thefirst clock signal ICK based on the emphasis control signal EMP<2>. Thesecond emphasis circuit 342 of the second driver 322 may invert thesecond output clock signal QCKO based on the second gating clock signalPQCK, and couple the inverted signal with the second clock signal QCK.Since the second output clock signal QCKO is a low level when the secondgating clock signal PQCK is enabled, a signal of a high level may beprovided to the second clock signal QCK and thus an emphasis operationfor the second clock signal QCK may be performed. Accordingly, therising edge of the second output clock signal QCKO may be generatedearlier than the rising edge of the second clock signal QCK, and thesecond output clock signal QCKO may have a pulse width wider than thesecond clock signal QCK. In FIG. 4, the second output clock signal QCKOmay be enabled at a point of time earlier than the point of timeindicated by the dotted line. The serializer 220 may output BL6 as theoutput data DOUT in synchronization with the second output clock signalQCKO of which phase is advanced in comparison with the second clocksignal QCK. Therefore, the eye and/or valid window of sixth output dataDQ6 may be increased by a period by which the phase of the second outputclock signal QCKO is advanced, and the sixth output data DQ6 having thehigh level may be precisely outputted.

However, since BL6 is a high level (“H”) and the next successivelyoutputted data BL7 is also a high level (“H”) the data detecting circuit211 may sense that data of a high level is outputted after data of ahigh level is outputted, and thus might not enable the emphasis controlsignal EMP<3> associated with BL7. Additionally, since both of BL7 andBL8 have high levels (“H”), the data detecting circuit 211 might notenable the emphasis control signals EMP<3:4>, and an emphasis operationfor the third and fourth clock signals ICKB and QCKB might not beperformed. Therefore, BL7 may be outputted as seventh output data DQ7 insynchronization with the third output clock signal ICKOB which has thesame phase as the third clock signal ICKB, and BL8 may be outputted aseighth output data DQ8 in synchronization with the fourth output clocksignal QCKOB which has the same phase as the fourth clock signal QCKB.

FIG. 5 is a diagram illustrating a representation of an example ofoutput data outputted from a transmitting circuit in an ideal case, notusing a transmitting circuit of the present disclosure and using atransmitting circuit of the present disclosure. In an ideal case, firstto eighth output data DQ1 to DQ8 may be generated to have the same wideeye. In FIG. 5, each of the hatched portions may correspond to a dataeye. When the first output data DQ1 is a high level, as in the casewhereby a transmitting circuit of the present disclosure is not used, aphenomenon may occur, in which the eye of the first output data DQ1decreases. The level of output data is held at a low level or a highresistance state before the first output data DQ1 is outputted. In thecase where output data of the high level is outputted while being heldin the low level or the high resistance state, inter-symbol interferencemay severely occur. Thus, the eye or valid window of the first outputdata DQ1 may be decreased. The transmitting circuit 200 in accordancewith the embodiments may perform an emphasis operation for the firstclock signal ICK which is used in outputting the first output data DQ1,and may generate the first output clock signal ICKO which has a phaseearlier than the first clock signal ICK, as shown in FIG. 4. Since thefirst output data DQ1 is outputted based on the first output clocksignal ICKO which has a phase earlier than the first clock signal ICK,the first output data DQ1 may have a data eye wider than a transmittingcircuit which does not use the present teachings even in a situationwhere inter-symbol interference occurs, and thus, output data having aneye of substantially the same size as in the ideal case may begenerated.

While various embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare examples only. Accordingly, the transmitting circuit improving dataeye, the semiconductor apparatus and the semiconductor system using thesame described herein should not be limited based on the describedembodiments.

What is claimed is:
 1. A transmitting circuit comprising: a clockgeneration circuit configured to generate a plurality of output clocksignals by performing an emphasis operation for at least one among aplurality of clock signals based on at least one among a plurality ofdata; and a serializer configured to output the plurality of data asoutput data in synchronization with the plurality of output clocksignals.
 2. The transmitting circuit according to claim 1, wherein theclock generation circuit generates the plurality of output clock signalsby extending pulse widths of the plurality of clock signals.
 3. Thetransmitting circuit according to claim 1, wherein the clock generationcircuit generates the plurality of output clock signals by advancingphases of edges of the plurality of clock signals.
 4. The transmittingcircuit according to claim 1, wherein, when data having a high level isoutputted first among the plurality of data, the clock generationcircuit generates an output clock signal by performing an emphasisoperation for a clock signal with which the data having a high level issynchronized.
 5. The transmitting circuit according to claim 1, wherein,when data having a low level is outputted first among the plurality ofdata, the clock generation circuit generates an output clock signal byperforming an emphasis operation for a clock signal with which the datahaving a low level is synchronized.
 6. The transmitting circuitaccording to claim 1, wherein, when data having the other level isoutputted as the output data after data having one of a low level or ahigh level is successively outputted as the output data by a thresholdnumber of times, the clock generation circuit generates an output clocksignal by performing an emphasis operation for a clock signal with whichthe data having the other level is synchronized.
 7. The transmittingcircuit according to claim 1, wherein the clock generation circuitcomprises: a data detecting circuit configured to generate emphasiscontrol signals by detecting logic levels of the plurality of data; anda clock emphasis circuit configured to generate the plurality of outputclock signals by performing an emphasis operation for the plurality ofclock signals based on the plurality of clock signals and the emphasiscontrol signals.
 8. The transmitting circuit according to claim 7,wherein the clock emphasis circuit comprises: a gating signal generatorconfigured to generate a plurality of gating clock signals from theplurality of clock signals based on the emphasis control signals; and aclock driver configured to generate the plurality of output clocksignals from the plurality of clock signals based on the plurality ofgating clock signals.
 9. The transmitting circuit according to claim 8,wherein the gating signal generator outputs, when a specific emphasiscontrol signal is enabled, a clock signal which has a phase earlier thana clock signal associated with the specific emphasis control signal, asa gating clock signal.
 10. The transmitting circuit according to claim8, wherein the clock driver generates the plurality of output clocksignals by advancing phases of the plurality of clock signals based onthe plurality of gating clock signals.
 11. A transmitting circuitcomprising: a serializer configured to output n{circumflex over ( )}thdata in synchronization with a first output clock signal, output(n+1){circumflex over ( )}th data in synchronization with a secondoutput clock signal, output (n+2){circumflex over ( )}th data insynchronization with a third output clock signal, and output(n+3){circumflex over ( )}th data in synchronization with a fourthoutput clock signal; and a clock generation circuit configured togenerate the first output clock signal, the second output clock signal,the third output clock signal and the fourth output clock signal from afirst clock signal, a second clock signal, a third clock signal and afourth clock signal based on the n{circumflex over ( )}th data, the(n+1){circumflex over ( )}th data, the (n+2){circumflex over ( )}th dataand the (n+3){circumflex over ( )}th data, wherein n is an integer. 12.The transmitting circuit according to claim 11, wherein the clockgeneration circuit generates the first to fourth output clock signals byperforming an emphasis operation for at least one among the first tofourth clock signals based on at least one among the n{circumflex over( )}th data, the (n+1){circumflex over ( )}th data, the (n+2){circumflexover ( )}th data and the (n+3){circumflex over ( )}th data.
 13. Thetransmitting circuit according to claim 12, wherein an output clocksignal which is generated as the emphasis operation is performed has aphase earlier or a pulse width wider than a corresponding clock signal.14. The transmitting circuit according to claim 11, wherein, when datahaving a high level is outputted first among the n{circumflex over( )}th to (n+3){circumflex over ( )}th data, the clock generationcircuit generates the first to fourth output clock signals by performingan emphasis operation for a clock signal with which the data having ahigh level is synchronized.
 15. The transmitting circuit according toclaim 11, wherein, when data having a low level is outputted first amongthe n{circumflex over ( )}th to (n+3){circumflex over ( )}th data, theclock generation circuit generates the first to fourth output clocksignals by performing an emphasis operation for a clock signal withwhich the data having a low level is synchronized.
 16. The transmittingcircuit according to claim 11, wherein, when data having the other levelis outputted as output data after data having one level of a low levelor a high level is successively outputted as output data by a thresholdnumber of times, the clock generation circuit generates the first tofourth output clock signals by performing an emphasis operation for aclock signal with which the data having the other level is synchronized.17. The transmitting circuit according to claim 11, wherein the clockgeneration circuit comprises: a data detecting circuit configured togenerate emphasis control signals by detecting logic levels of then{circumflex over ( )}th to (n+3){circumflex over ( )}th data; and aclock emphasis circuit configured to generate the first to fourth outputclock signals by performing an emphasis operation for the first tofourth clock signals based on the emphasis control signals.
 18. Thetransmitting circuit according to claim 17, wherein the clock emphasiscircuit comprises: a gating signal generator configured to generatefirst to fourth gating clock signals from the first to fourth clocksignals based on the emphasis control signals; and a clock driverconfigured to generate the first to fourth output clock signals from thefirst to fourth clock signals based on the first to fourth gating clocksignals.
 19. The transmitting circuit according to claim 18, wherein,based on the emphasis control signals, the gating signal generatorgenerates the first gating clock signal by using the fourth clocksignal, generates the second gating clock signal by using the firstclock signal, generates the third gating clock signal by using thesecond clock signal, and generates the fourth gating clock signal byusing the third clock signal.
 20. The transmitting circuit according toclaim 19, wherein the clock driver comprises: a first driver configuredto generate the first output clock signal by buffering the first clocksignal, and feed back the first output clock signal to the first clocksignal based on the first gating clock signal; a second driverconfigured to generate the second output clock signal by buffering thesecond clock signal, and feed back the second output clock signal to thesecond clock signal based on the second gating clock signal; a thirddriver configured to generate the third output clock signal by bufferingthe third clock signal, and feed back the third output clock signal tothe third clock signal based on the third gating clock signal; and afourth driver configured to generate the fourth output clock signal bybuffering the fourth clock signal, and feed back the fourth output clocksignal to the fourth clock signal based on the fourth gating clocksignal.